Formal Verification
نویسنده
چکیده
Formal verification (FV) involves the use of logical reasoning to establish properties of a computer program (or hardware element, protocol etc.) In the purest form of FV, rigorous logical deduction is used to prove with full mathematical rigor that the program satisfies a logical specification. This is often contrasted with the traditional approach of testing on a variety of specific inputs or situations, which may be a useful way of increasing confidence and catching bugs, but is usually not completely exhaustive or conclusive.
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تاریخ انتشار 2011